END CAP CELLS

Background:

When you integrate partitions/sub layouts at IP level or IPs at SoC level, you would need to align with certain boundary conditions so that integration become seamless. Process team/Fab comes with certain requirements of well alignments/well rings on layout boundary. Ideally speaking if the designer knows the alignment DRC , he can draw well rings/sometimes metal around the boundary to meet process requirements. To ease this job, process team/library teams provides Special Physical Only Cells which must be used by all designs so that integration work becomes correct by construction.

There are different perspectives about end cap cells. Some foundries design end cap cells to help DRC alignment where as some other companies design with DECAP in them so that they act as decoupling capacitors for the site rows where they are placed.

End cap cells are placed on both ends of the horizontal site rows and also placed on top & bottom edges (nwell, DRC requirements). When these cells are placed on boundaries of a partition/sub design,we are ensuring that the integration at higher level will not see any abutment problems.

Types :

i) Horizontal End Cap Cells (at both edges of site rows)
ii) Vertical End Cap Cells (along the horizontal edges/rows of the design )

(Sometimes designers can have a third type of cell to be placed in corners - Corner End Cap Cells)

     

Look at the sample image above which shows about how horizontal end cap cells are placed on left and right boundaries of the chip/IP/Sub block. Similarly you can imagine vertical end cap cells,corner specific cells

How to insert and at what design phase ?
If you are using IC Compiler : Explore "add_end_cap" command

The best phase is to insert end cap cells right after the floorplan is decided (as part of pre place cells).