If we look at the std cell pin hold requirement: usually this number is positive.That means it expects data not to change till certain period past the active clock edge (th) as shown in the below image:
This may not always be the case.There are scenarios where the path from the pin of flipflop (data) to to the internal latch point is longer than the corresponding path of the clock (to the regular ckt) - finite amount logic exist within std cell on data path (i.e data pin to actual point where data get sampled )
Take a look at the below image:
Here data pin to regular ckt we see 9ns of logic, which delays data further by 9ns
In such cases, std cell team comes up with a negative hold requirment at data pin wrto clock something around : -9ns + 2ns ==> apporx -7ns
Note : The above explanation is very basic (similarly for setup as well if there is a delay in clk path !!) and i will be going to write a detailed article in future.
This may not always be the case.There are scenarios where the path from the pin of flipflop (data) to to the internal latch point is longer than the corresponding path of the clock (to the regular ckt) - finite amount logic exist within std cell on data path (i.e data pin to actual point where data get sampled )
Take a look at the below image:
Here data pin to regular ckt we see 9ns of logic, which delays data further by 9ns
In such cases, std cell team comes up with a negative hold requirment at data pin wrto clock something around : -9ns + 2ns ==> apporx -7ns
Note : The above explanation is very basic (similarly for setup as well if there is a delay in clk path !!) and i will be going to write a detailed article in future.
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