UNINTENDED LATCHES

Background:

Sometimes the way you write RTL code infers Synthesis tool to insert a latche in a place where you thought of implementing a combinational logic such as multiplexer. Those types of latches are called as Unintended Latches (since you did not code them intentionally !!)  or also called as Inferred Latches (assumed by Synthesis tool !!). These are coming in design by accident, so you can call them as accidental latches :-)

Details:

A latch is inferred within a combinatorial block where the net is not assigned to a known value. Assign a net to itself will still infer a latch. Latches can also be inferred by missing signals form a sensitivity list and feedback loops.

 --> Missing one of the input combinations in a case/if statement forces synthesis tool to infer latch for missing combination. 
Here for "a = 11 case" 

always @*
begin  
case(test_a[1:0]) 
  2'b00:  test_o = 1'b0; 
  2'b01:  test_o = 1'b1; 
  2'b10:  test_o = 1'b1;  
endcase
end

What it means for physical design engineers ?
Once synthesis is completed, review the latches implemented in the design and understand if any of those are not intended per design requirements.Report such issues to RTL team to get them addressed. Ideally speaking; these won't come at all if they pass all LINTRA checks(LINTRA is a RTL lint tool to verify design issues like inferred latches or unloaded inputs etc..)