INDUCTANCE IN SPEF

I  always wondered why we just extract R & C for parasitic estimation of interconnect segments and will not consider L for extraction.
I mean this is okay : but every net has to be broke down into combination of R, L & C for accurate modelling right ?  in vlsi chip design), we have to consider three basic impedance parameters right ? I mean R., L & C. 
But why do we just take R, C and do sign-off closure wo L . 

Some insight into the reason is :
(please be aware that the explanation here is very generic and I will be updating a detailed article soon..)

Inductance is important at high operating frequencies for long nets, such as clock nets or any dedicated routes that have really huge length. A regular signal strength can face overshoot, undershoot, spikes, bumps in it and increased skew for clock nets etc..

Impedance of a general net segment  :

Z  = R + jwL + (1 /jwC)   ; (w  proportional to freq of operation )

R  :   Resistor component is default 

C  :   Capacitance impact is also unavoidable due to 

  C  = €A/d  ( spacing between two metals or metal to ground/substrate can be denoted as d)

Since d is approaching to very small value as the VLSI is packing more devices in small areas, self-capacitance and coupling capacitance are dominating at advanced nodes

L :  Inductance effect comes in 

 i) to picture when width of the interconnect is more or frequency is high.

 ii) when frequency is high 

 iii) when width increases resistance decreases, it will dominates inductance terms.

Some parasitic engines provide option to opt for the Inductance extraction also.
(Star RC etc.. for critical clock net inductance extraction)

For all Digital designs which are pretty much routed by Tools have lot of small net segments which in-turn cannot create too much of inductance- So we won’t consider inductance component  ( unless if it’s really matter for specific nets )

But  now the trend is changing :

 As technology advances into  single digit nanometer era, interconnection delay dominates overall circuit performance and  disturbance/noise is a considerable impact than earlier days.  So if we do any optimistic analysis of interconnect characteristics/noise modelling then performance of designs become questionable.  It’s like considering R,L,C vs R,C to model delay, noise char for a net segment. Of course we lose the accuracy if we drop L but to what extent ? This is what the key for all modelling tools ( Star RC etc..). 
If the modelling b/w R C vs R L C has significant change : then the device char will go for a toss. As die size increases, quick slews of signals and long wires make inductance effects much more significant than older days. So now people start considering self and coupling inductance effect (again based on their design statistics..)