PROCESS NODE

Alternate terminologies of Process Node  : Technology Node or Semiconductor Process node

• Smallest Half -Pitch of contacted Metal 1 lines [lowest metal in that process] that can be feasible/allowed in the fabrication process.  VLSI fabs, companies use this term as a parameter to measure/denote the advancement in fabrication process.
• Smaller the node --> denser the devices --> more computing logic in less area --> more functionality --> faster and lower power per function
• Important thing to note here is : Let's say 16nm processor, should have half metal1 pitch as 16nm, but that's not always the case at lower/advanced nodes: Companies are started calling approx. numbers as per marketing mantra. It does not correspond to any gate length or half pitch. But it's almost around the quoted number
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• Concept was raised previously due to the denser memory requirements [DRAM]. Since denser memories are dependent of process scaling, ITRS came up with initial metric to direct the technology advancement.
• Still this number is more a process name than the actual measure of any exact physical  feature
• Two ways of looking at technology node concept :
• If we are talking about mobile SoC/PCs etc.. : technology node is the half pitch between two adjacent DRAM metal lines. Now this doesn’t correspond with the Lmin of a MOS transistor and so you have to take this definition with a pinch of salt. For example when a company focused on digital applications says its working on 17 nm technology, then it most probably means this DRAM half pitch, as that is the minimum feature size that can be “printed” by the lithography technique adopted by that company(which of course is less than the transistor Lmin in this case). 
• If we are talking about Analog Mixed signal applications : Where they employ BCD processes(Bipolar DMOS, CMOS) the book definition is not applicable. So if a person from such a company says he/she is working on 130 nm node for example, then it might not mean that the DRAM half pitch is 130 nm as they might not be using DRAM’s at all! In such cases it can be safely assumed that the 130 nm is the Lmin of the MOSFET’s used in the process. Initial definition : Smallest feature was almost always the line that defined the gate electrode on the MOS transistor. So the name of a process became identified with the width of the gate electrode.Just to make matters more complex, designers referred to this as the "gate length." (If you look at a transistor the way the current does, from one end through to the other, the width of the gate electrode determines the path length the current must traverse getting through the channel region.) Unfortunately for clarity, the gate length is also an approximate measure of transistor speed and of how densely you can pack transistors together in a hand-crafted layout.

Thanks to EDN web for the below data:

• Marketing departments seized upon the term as a measure of goodness, and quickly turned what had been a measure of a physical dimension into a measure of marketing bravado. The result was that by about 350 nm (actually called 0.35 micron in those days), the "350 nm" had become simply the name of the process rather than a measure of any physical dimension. The process might only be able to resolve a 380-nm line width, but through various other tricks, process engineers could get the transistors to behave as if their channel length were 350 nm. So it goes.
• Today, the number has recovered some accuracy as a physical measure. A 65-nm process usually does have features—again, usually gate line widths—that are approximately 65 nm. There are exceptions. For instance, a company might design a process that will eventually be able to produce 65-nm lines, but for economic reasons they will leave out one or two critical pieces of equipment that would be necessary for the finest possible lines. They will usually announce this as a "65-nm" process, even though today it can't do 65-nm features.
• The fascinating part today is that it is physically impossible for the printers, which work with 193-nm-wavelength light, to accurately transfer a 65-nm line from the mask to the wafer's surface. So designers use incredibly sophisticated tricks to make patterns on the mask that, when blurred and distorted by diffraction in the printing process, will end up being sort-of credible 65-nm-wide lines. These tricks include attaching "decorations" all over the line on the mask—bulges in the center, little whiskers at the corners, things that make a rectangle look more like an image in an ink-blot test. This in turn means that even if you can make one perfectly acceptable 65-nm-wide line, you may not be able to make another one right next to it. You may have to leave room for decorations in between. So today, "65 nm" or "45 nm" doesn't exactly refer to the line width, and certainly doesn't indicate how closely you can pack transistors together, although it does provide some indication of these things. Still, it is probably most accurate to say that the number is simply the name of the process, rather than the measure of any particular feature