Xilinx

XILINX:[5 rounds ] : [3.5 + yrs RTL2GDSII engineer position]
1. PD flow overview and question randomly on some of the steps
2. Antenna diode concept, physical layout view:
3. How to avoid antenna effect : how many ways : which is optimal at what process of the design ?
4. Challenges in floorplan, placement you had faced ?
5. Clock tree exceptions : how do give an early clock to SoC  etc.. ?
6. Latch timing analysis challenges
7. Setup and hold concepts
8. How to tackle macro placement challenges  ?
9. Synthesis related :
1. Why only setup analysis but not hold
2. After scan insertion : do you use compile incr ? If so why ?
10. Scan chain reordering :
1. Reg scan def and how can icc come up with a new re-order and why ?
2. Scan flop vs regular flop architecture dff
3. Scan shift vs scan capture . Need for scan and general operating range of  scan mode
11. Fev :
1. Syn vs rtl -challenges
2. Apr vs rtl   against apr vs syn ? Key difference ? 
3. Why do we disable scan paths during fev ? How do you make sure those are validated ?
4. Flow overview : key points , map points , logic cone concept
12. How to tackle high freq paths in synthesis ?
13. Register Re timing , register array concepts.  Multibit array.
14. Flop clone/merge - challenges in fev - how to guide fev tool ?
15. Max delay vs fp vs mcp vs max tran vs max cap priority for PD tools ?
16. Path grouping examples- how does it work vs critical range. TNS vs WNS cost factors for PD tools ?
17. TCL scripting related basic questions . Any utility you developed and its overview ?
18. Tran requirements on your most recent project ? Why do you choose such numbers ?
19. Jitter, skew etcc - clk uncertainty . Effects of these pre/post layout ?
20. MCMM concepts - basics only
21. Assume that you are starting a new project - list out the steps on how to develop full full chip constraints from scratch
22. Clocking concepts - latency , any special cares in PD ?
23. Details on some of the current projects and experiences ?
24. Check timing - un expandable clocks , UCEP reasons etc.. ?
25. Min pulse widths ? Where does this req come from ? IP specific or freq specific or cell behavior specific? Will .libs are modelled with it ?
26. Why special cells for clk tree ?
27. Number of clocks, macros and the complexity of your recent projects ?
28. List of tools you have experienced on and at what level ?
29. Internship project details - Why didn’t u join Synopsys post your internship instead of moving to Intel ?
30. Why do u want to relocate to hyd ?
31. Current CTC ? Expected CTC ?  How do you justify such % hike ? What difference can you make ?
32. Some other behavioral questions