Qualcomm

    QUALCOMM:[4 rounds]:[4+ yrs RTL2GDSII engineer position]

    1. Masters projects overview
    2. Internship project related questions
    3. SRAM basics
    4. Grouping of cells to meet certain physical requirements - commands and some details
    5. RTL2GDSII design flow : each stage from synth-compile-logic-opttimization-path-grouping-floorplan-placement-cts-route-chip_finish:       details of those
    6. Special cells ? Tap , decap : reason for usage ? Internal  structure ?
    7. How to handle high frequency paths ?
    8. Target lib subset related : restrict  libs based on hierarchy : timing vs power vs area req ?
    9. Area / Power recovery from an almost closed  design ?
    10. Threshold voltage vs Current vs Delay vs lower tech node inter related questions: like how does delay get impacted with threshold, temp inversion etc..
    11. LVS : types of issues faced and effective solutions used ?
    12. Current project details : specification and real world application examples ?
    13. Various types of physical verification runsets : brief overview ?
    1. FEV basic concepts
    2. power switches 
    3. multi vdd designs , voltage areas and power grid design examples for such cases
    4. gated domain vs aon domain  details. Why there is a need for upf etc..
    1. Extraction :
      1. Details on extraction back ground
      2. Extraction corners : typical vs rcbest  vs cbest vs cworst etc..
      3. Conceptual differences bw extraction corners
      4. Cworst vs rcworst : will there be aby R component in Cworst ?
      5. Can you draw a physical metal shape and show us the behavior in each corner ?
      6. Do you know if voltage also used as one of the parameter while doing extraction [like for std cell pvts ?]
                                             Answer: we don’t do extraction based on voltage. Only corner and temparature are the key parameters. 
                                             g. Does that mean rcworst @ 125 degrees @ 1.1 v  ==>  rcworst @ 125 degrees @ 1.3 v  . Yes..
    1. Cross talk :
      1. Agressor vs victim : diagrams, examples
      2. Set_false_path vs set_case_analysis impact/prime time assumptions on cross talk/noise modelling ?
      3. Hold , setup dependency wrto cross talk ?
      4. Crosstalk effects on a function timing path due to scan path and mbist paths ? How does it changes ? Reasoning etc..
      5. Techniques to avoid cross talk : shield , spacing . Differences. Which is best ?
    2. Clk NDR related. Clk net routing at what layers ? Why you choose only those ?
    3. Number metal layers in your most recent design ?
    4. Some sample image like below :

                            Image result for path groups vlsi
    Questions on how to constrain this design: list of commands at what ports etc..:
    like writing constraint for each port/clock/set_false_path/io delay
    1. False path, mcp example diagrams. MCP details -start, -end etc..
    2. How an actual MCP can occur : from design side : high freq to low freq paths or vice versa OR huge adder/multiplier logic bw lauch and capture details..
    3. Why do you want change your company ?
    4. How soon can you join us ?
    5. They explained about work profile and asked if any concerns

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