SYNOPSYS [ 3.5 yrs + ] : [Sr R&D Engineer - (RTL2GDSII domain)]:
1) Tell me about yourself ?
2) What is the tech file ?
a. What it contains : Can you share the internal details ?
b. Did you ever edit tech file to meet your requirements ?
c. In what all flows you use it ?
3) Why PT timing differs from ICC timing analysis ?
a. Key differences
Answers : timing algorithm under the hood , ICC uses extract_rc based on tlu + files where as spef input to PT is from detailed star rc based extraction
4) Clock tree exceptions : how to balance the clock : stop vs exclude/ignore vs float pin
5) If a signal is being used as a clock to flops and also going to output ports . Then will CTS balance the output port vs flop clk pin ?
Answer : No, we must define a stop/float pin based on our requirement
6) What are the cases where we generally see CTS issues :
a. MV CTS and CTS on don’t touch nets ?
b. If there is no clk attr/definition on macro clk pins and input clk port is directly driving that port, how does the CTS tool behaves ?
c. If for some reason CTS isn't inserting any CTS buff : what could the reason be ?
i. Worst-case how do we any temporary fix ?
7) Can you talk about .lib internals and if you can : can you write a sample .lib format of a flip flop ?
8) What was the desin implementation strategy you had followed for an IP ?
a. Like modular vs flat vs mixed ? How did the decision happen ?
b. Which is the best way ? Is it like implementation is hier and sign-off is flat ? Details ?
9) TLU+ files ? What are those ? Usage ? Details ?
10) DC - TOPO vs WLM ?
a. Type of WLMs calculation ? What does internal WLM contain ?
b. TOPO mode : critical inputs required ? Why TOPO ? Accuracy of results ?
c. Coarse placement happens in dc_top "spg mode" : can feeding this def as a baseline input to ICC or start fresh placement
11) IR drop , EM, SH, details ?
12) IR drop depends on what all parameters ?
a. Details on power grid structure ? Mesh vs ring ? Why so ?
b. How come you decide number of straps/spacing of power grid ?
c. What was the general limit of IR drop on a power net ? 10% of VDD ?
d. Which tool you had used ? What are the inputs to IR and EM flows ?
e. Any techniques to fixed EM, SH, IR ?
13) What is your current working spectrum : which all flows/domains you can handle ?
14) Do you have any questions to ask us ?
15) What all SDC contains ?
Details : clk, delay, fp, mcp async constraints, tran, cap, load & latency etc..
16) How to constrain feed through paths ?
a. set_max_Delay vs i/o delay using a vir clock : which is better approach ?
17) How IO constraints affect logic optimization ?
18) How to constrain a design : at min we need clocks - to have reg2reg paths constrain. And i/o delays for i/o logic constraint
19) Need of set_driving_cell ? Why do we use this so ? Can't we just some flat tran number at input ports and leave it ?
20) Cross talk effects and ways to fix ?
21) Tcl script to reverse a file content
22) Tcl script to sort an array or list ?
23) Collection vs list vs array ?
24) Half cycle path talk ?
25) How to fix min-max paths ? Why do they arrive ? Best design practices to avoid such cases?
26) UPF details : internals and need for UPF ? Low power strategy?
27) Why do you want change job ? Where are expecting in 5 years ?
28) Expected compensation ?
29) What are your biggest achievements ?
30) Can you talk about full PD flow in each detail ? Key steps/challenges in each stage ?
31) CTS details - ICG , gen clk vs master clock balancing ?
32) CTS - design rule fixing vs balancing priorities ?
33) Did you try any scripts and its objectives ?
34) How do you give rating to yourself on each flow and tool ? On a scale of 1-10 ?? :-)
35) Given a design/PT session having lot of timing issues: what are the ways you start and arrive at closure plan?
a. Order of issues you focus ? Why ?
b. Details on link lib vs target lib
36) Target lib subset related questions ?
37) Inputs to PT ? Did you use UPF based approach ? If so why you use UPF ? : we use " upf + pg netlist "
38) ECOs :
a. Steps , BKMS ?
b. Did you work on DMSA flow based eco generations ?
39) How can you fix tran, cap violations ? In what order do you fix viol : tran, cap, setup & hold ?
40) Cost priority settings ?
41) Why do we use filler cells ?
42) Critical challenges you had faced in physical verification :
43) Types of lvs issues you saw ?
44) 10nm vs 14nm vs 28nm what are the key differences b/w technologies ? Device vs interconnect delay changes ?
45) Antenna concept in detail ?
46) Latch up in detail ?
47) Macro placement related concepts ?
48) What all thing you check in each stage as a better design practice ?
49) LVS details : inputs and how does flow actually does comparison ?
50) What are the general recommended settings of tran for clk and data networks and why clk tran setting is tighter ?
51) Does your .lib has power consumption of a cell ? If yes what type of power is that ? (only leakage /shortckt etc.. ) ?
52) What are the ways you do power calculations of a design : PTPX : using VCD covering all corner cases :
a. REDHAWK also dumps power numbers of the design ? : yes but these are only worst case numbers [since no vectors are provided]
b. VCD : PTPX related couple of questions
53) Power consumption details : leakage / short ckt / dynamic power etc.. At 14nm/10nm what are the critical components : better way to avoid ?
54) About masters project - core objective ?
55) Couple of RTL and digital basics -[internship was in logic design , so]
56) Related to GDS/stream file : flat or hier ? What kind of challenges driven you to debug issues on stm directly instead of mw ?
57) Can you tell us the lef file format and sample of a cell structure syntax ?
a. If I give a lef file of 22nm std cells package : can you directly use any special way to grep/list out all filler cells ?
b. Def vs lef ?
58) Why do we buffer all signals coming in and going out right at the ports ?
59) Create buffer tree related ?
60) Ideal network and HFN, gen clock , propagated clock means etc..
Thank you
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