Technology
File is the most critical input for physical design tools. If you want to start
any further steps or create a mw lib to start any further in physical design ?
You must have tech file ready in your hand. Many companies start preparing
their own tech file based on design rule runsets provided by foundry for that
specific technology node or sometimes tech file comes as part of stdcell team.
In a nut shell : It
provides technology-specific information like the names and physical and
electrical characteristics of each metal/via layers and the routing design
rules.
It guides physical design
tool on below list of information:
- Unit tile definitions that can be used in site rows so that placement engine can guide placement of cells ?
- List of metals available for routing ?
- Metal widths, spacing & pitch info etc.. ?
- Design rules between same metal layer spacing ?
- What are all the via types/via masters available ?
- Units of length, cap, power, resistance & technology precision etc.. ?
Not only the
listed factors above but tech file supports many other foundry guidelines and
other useful physical design info. I would like give details by using a sample
snippet of tech file below.
Details :
- To write out the existing tech file from icc_shell : icc_shell> write_mw_lib_files -technology -output techfile.tf
- File extension is ".tf" ; # not a hard rule :-)
- A technology file consists of several sections, each of which uses the following syntax:
section_name
{
attribute_name = attribute_value…
}
I'm listing down some of the important sections of
tech file.
Note :# There are many other sections in .tf . Depending on
the complexity of fab rules and requirements, those extensive list can be
used.If you have solvnet access , I would encourage you to read the following
documents for detailed description.
There is lot of useful stuff at
1) Synopsys Technology File and Routing Rules
Reference Manual:
https://solvnet.synopsys.com/dow_retrieve/L-2016.09/iccolh/Default.htm#icctf/icctf.html
https://solvnet.synopsys.com/dow_retrieve/L-2016.09/iccolh/Default.htm#icctf/icctf.html
2) Technology File Syntax :
https://solvnet.synopsys.com/dow_retrieve/L-2016.09/iccolh/Default.htm#icctf/icctf_1.html
https://solvnet.synopsys.com/dow_retrieve/L-2016.09/iccolh/Default.htm#icctf/icctf_1.html
3) 32nm and Below Design Rule Support in IC Compiler
- Zroute:
https://solvnet.synopsys.com/retrieve/031863.html
https://solvnet.synopsys.com/retrieve/031863.html
* : The numbers
below are random and does not convey any process specific. Just took for the
sake of explaining..
Section 1 :
#----------------------------------------------------#
#Below section
contains details of the technology : like name, units, precision of grid etc..
#----------------------------------------------------#
Technology {
name
= "65nm" ;
# name of the technology
date
= "2016/10/22" ;
# date on when this file got updated ?
dielectric
=
<value?> ;
# value of di electric constant of this technology ?
unitTimeName
=
"ps" ;
# time units : though units from .lib are used for timing analysis, we still
need to keep here for consistency !!
timePrecision
=
1000 ;
# timing precision, you can go on till 100ps , later 1ns ?? details pls ?
unitLengthName =
"micron" ;
# physical dimension units
lengthPrecision
=
1000 ;
# precision of the physical drawn length ?
unitVoltageName =
"V" ;
# voltage units : volts ==> V
….
….
unitCapacitanceName
=
"ff" ;
# capacitance units : femto farad
capacitancePrecision
=
1000000 ;
# details ??
....
….
}
Section 2:
#----------------------------------------------------#
# Declare all type
colors you may use in the design, red, gree, blue etc.. (RGB)
# Once you go to
metal layer definition section, you can assign these colors for metals using
"color" options
#----------------------------------------------------#
Color 1 {
name
= "chocolate"
rgbDefined
= 1
redIntensity
= 100
greenIntensity
= 150
blueIntensity
= 200
}
Section 3:
#----------------------------------------------------#
# TILE definitions :# Most important info: unit
tiles : based on these ICC site row definitions and std cell placement happen
# Can contain more
than one type of tiles to accommodate diff scenarios
#----------------------------------------------------#
Tile
"unit" {
width
= 0.5 ;
# min lego width : X lego value
height
= 0.6 ;
# min lego height : Y lego value
}
Tile
"core" {
width
= 0.5 ;
# same as above
height
= 0.6 ;
# same as above;
*
we can various tile declarations as per need, while creating site rows, use
corresponding tile definition
}
Section 4:
#----------------------------------------------------#
# Layer details:# details of layers : metal,
via, diffusion , etc..: it contains : layer number , name , color, pattern, min
width, pitch, etcc . drc wrto next metal/via */
#----------------------------------------------------#
Layer "m2"
{ ;#
layer details start: layer is m0
layerNumber
=
xx
;# layer number that will get shown on options while doing layout edits :
;#
you can say stream compatible number which gets used for lvs reporting etc.. */
maskName
= "metal3" ;# mask
name , can be used for verify_lvs and also tech2itf comparisons. but m0 is the
std names used for icc visual/internal routing
isDefaultLayer
=
1 ;#
to denote if this is the default layer that ICC can use for physical
implementation
color
= "red" ;# what color
do you want see this metal or layer ?
pattern
= "dot" ;# what
pattern : fill or dot or lines for this layer ?
lineStyle
= "solid" ;# boundary
line is solid ? or transparent etc..
visible
= 1 ;#
is it a visible layer ?
pitch
= 1 ;# layer pitch, distance between center to center
of m0 shapes that can be allowed
minWidth
= 0.5 ;# min width of the layer that can be drawn
by ICC
defaultWidth
= 0.5 ;# what is the default width of the the
layer ?
minLength
= 0.5 ;# how much is the min length of m0
can be drawn ?
xMinSpacing
= 0.5 ;# what is the min spacing in x direction that
another m0 can sit ?
yMinSpacing
= 0.5 ;# what is the min spacing in y direction that
another m0 can sit ?
cornerMinSpacing
= 0.5 ;# m2 to m2 corner in another track allowed
distance at min is ?
minSpacing
= 0.5 ;# details ?
..
nonPreferredRouteMode
= 1 ;# to denote ICC whether m0
can be used for non - preferred direction routes if required ? 1 ==> no
non-preferred routing, 0 : routing can be in any direction
orthoSpacingExcludeCorner =
1 ; # 1 means check only corner
2 corner space, not x and y as well
onWireTrack
=
1 ;#
details ?
yLegalWidthTblSize
=
4 ;#
details ? : what can be the width of table
yLegalWidthTbl
= (0.5,0.6,0.7,0.8) ; # 0.046) * details ?
}
#----------------------------------------------------#
Layer "v2"
{
layerNumber
= xx
maskName
= "via2"
isDefaultLayer
= 1
color
= "blue"
pattern
= "solid"
minWidth
= 0.5
minSpacing
= 0
defaultWidth
= 0.5
maxStackLevel
= 10
onWireTrack
= 1
cutTblSize
= 4
cutNameTbl
= (CUT1A, CUT1B,CUT1C,CUT1D)
cutWidthTbl
= (0.5,0.5,0.5,0.5)
cutHeightTbl
= (0.25,0.25,0.25,0.25)
enclosedCutNumNeighbor =
3
/* Enclosed cut rules */
fatTblDimension
= 4
/* list
down all fatTbl related rules */
}
Section 5:
#----------------------------------------------------#
# Via Contact Codes# Via master properties like
layers, resistance, enclosure etc..
#----------------------------------------------------#
ContactCode
"VIA2AB" {
contactCodeNumber
= 1
cutLayer
= "via2"
lowerLayer
= "m1"
upperLayer
= "m2"
isDefaultContact
= 1
cutWidth
= <value>
cutHeight
= <value>
upperLayerEncWidth
= 0.1
upperLayerEncHeight
= 0.0
lowerLayerEncWidth
= 0.1
lowerLayerEncHeight
= 0.1
minCutSpacing
= 0.0
unitMinResistance
= 0.1
unitNomResistance
= 0.1
unitMaxResistance
= 0.1
}
Section 6:
#----------------------------------------------------#
#Via Cut Spacing Rules# list all DRs between
tow cuts : within same layer or with adjacent layers (via set like v1-v1 and v1
<--> v2 etc..) that are used for ICC routing engine.
# general set of
rules are : edge-edge, corner to corner and center to center of vias
#these rules can be
between same net cuts (sameseg, samenet rules) or diff net cuts ( like if the
cuts don’t share any immediate upper/lower metal - diffseg, diffnet rules
#As of 2012,
Synopsys ICC tech file was supporting 16 via cut rule types
#----------------------------------------------------#
DesignRule {
layer1 =
"Via1"
layer2 =
"Via2"
cut1TblSize = 4
cut2TblSize = 4
cut1NameTbl = (Vsm,
Vv, Vh, Vlg)
cut2NameTbl = (Vsm,
Vv, Vh, Vlg)
sameNetXMinSpacingTbl
= (S11,S12,S13,S14,
S21,S22,S23,S24,
S31,S32,S33,S34,
S41,S42,S43,S44)
diffNetXMinSpacingTbl
= (D11,D12,D13,D14,
D21,D22,D23,D24,
D31,D32,D33,D34,
D41,D42,D43,D44)
}
All
text between /* and */ is ignored.
Note : orthoSpacingExcludeCornerTbl = (1) ; #
specify this if both edge-edge and corner-corner rules are present and you want
the tool to consider only corner-corner rules
Can you give picture for viacontact code and mention values defined in .tf(synopsis) file
ReplyDeleteAnd picture for via in .tech(cadence) file
Nice Blog. Thanks for sharing
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